The present invention relates to a semiconductor integrated circuit operating at a low voltage and a high speed, and particularly to a semiconductor integrated circuit capable of stabilizing an operating power supply.
In a semiconductor integrated circuit, power supply wiring and ground wiring, which are sufficiently decreased in resistance, are laid in the circuit, for supplying a specified voltage to each element and stabilizing the operation of each element in the circuit. However, when high power consumption locally occurs in the semiconductor integrated circuit, a power supply voltage is instantaneously decreased in its vicinity. As a result, operation errors in logical circuits or jitters in output signals occur. Such a phenomenon significantly occurs in a semiconductor integrated circuit operating at a high speed and a low power supply voltage.
Methods generally used for resolving these problems include those in which power supply wiring and ground wiring are strengthened, i.e., wiring is thickened to decrease the resistance, and those in which a capacitor is formed between a power supply and a ground, in order to stabilize a power supply voltage for instantaneous power consumption. Examples of these methods are known as below:
(1) One of a top metal wiring layer (layer n) and a wiring layer (layer n−1) directly below the top metal wiring layer is connected to a high-voltage power supply VDD. The other is connected to a low-voltage power supply VSS, and an insulating material having a relatively high dielectric constant is formed thinly between these two wiring layers. As a result, a capacitor cell is formed which stabilizes a power supply using the wiring layers of n and n−1 as electrodes. (Japanese Laid-open Patent Application 2002-270771).
(2) The wiring layers of M1, M2, and M3 are laminated so that the pitch array direction of a plurality of wirings arrayed at a pitch in the same direction crosses that of a plurality of other wirings arrayed at a pitch in the same direction. The wiring layers of M1, M2, and M3 are connected to each other so that potentials VDD and VSS are supplied to the adjacent wirings in each of the wiring layers M1, M2, and M3. As a result, decoupling capacitance is formed between the adjacent VDD and VSS wirings in each of the wiring layers. (Japanese Laid-open Patent Application 2003-249559).
However, in the method disclosed in JP 2002-270771, a capacitor cell to power supply wiring is usually required to be added. Therefore, it has the problem of requiring two wiring layers and increasing the manufacturing cost compared with a general semiconductor integrated circuit.
In the method disclosed in JP 2003-249559, a capacitor between the VDD and VSS wirings in the same layer is formed. It has the problem that it cannot provide sufficient electrode area from a structural point of view, and causes difficulty in securing enough capacitance, and particularly the problem of failing to form a large capacitor when the number of signal wirings is increased.